1. Field of the Invention
The present invention generally relates to a high-speed data buffer, and more particularly, to a data buffer applicable to a single data rate buffer adopting either the rising edge or the falling edge of the clock signal and also a double data rate buffer adopting both the rising edge and the falling edge of the clock signal. Such a high-speed data buffer is suitable for use in high-speed data communication systems.
2. Description of the Prior Art
In recent years, as the demands for a higher speed of data processing and a higher frequency for operation in the computer system continuously increase, designers of high-speed circuits have often encountered problems due to insufficient processing timing margin. Therefore, it has become an important topic to well control the timing of the rising edge and the falling edge of the clock signal.
On the other hand, IEEE-1394 has become a standard for communication interface for future digital information products since Japan-based superpowers of electrical/electronic products have promoted the applications of IEEE-1394 in digital information products. Nowadays, IEEE-1394 has been widely adopted in the state-of-the-art digital cameras such as DV and D8 in Japan, the United States and Europe, and therefore the research and development of the related communication products has drawn a great amount of interests.
Accordingly, the applications of high-speed transfer data in combination with the IEEE-1394 Series Bus have attracted the industry's investment. For an exemplary embodiment of the prior art, when the receiving end of the physical layer of the IEEE-1394 Series Bus is to be operated at 400 Mbit/sec, the data with a 200 MHz clock is decoded and then delivered (due to the double data rate). When the receiving end receives the data and the clock signal, in the worst case, a clock cycle can be as short as 3 ns (nano-second) and a clock pulse can be as short as only 0.6 ns because of jitter and skew generated during the process in which the data and the clock signal pass through the cable or other circuit elements. For 0.35 μm process, the clock-to-output of a flip-flop takes about 0.6 ns to 1 ns. Therefore, the receiving end meets a serious problem in that insufficient timing leads to an error when the data are input into the data buffer. The explanation is described hereinafter.
Please refer to FIG. 1, which shows a circuit diagram illustrating a conventional data buffer in the prior art, exemplified by a 2×2 double data rate buffer, wherein the buffer circuit is structured to form a falling-edge-triggered ring counter. Such a data buffer comprises a first D-type flip-flop 2 with the negative output coupled back to the D input, forming a clock output circuit; and a second D-type flip-flop 4 and a third D-type flip-flop 6, forming a falling-edge-triggered ring counter, wherein the first flag signal FLAG1 represents the output of the second D-type flip-flop 4 and the second flag signal FLAG2 represents the output of the third D-type flip-flop 6. The positive output of the third D-type flip-flop 6 is coupled back to the D input of the second D-type flip-flop 4 so as to form a ring counter.
FIG. 2 shows two sampling circuits. In particular, FIG. 2A illustrates a first rising-edge sampling circuit operative for generation of a first sampling clock signal CLK1, wherein said first sampling clock signal CLK1 is generated by an AND operation of the clock signal and the first flag signal FLAG1 provided by a first AND gate 12; while, similarly, FIG. 2B illustrates a second rising-edge sampling circuit operative for generation of a second sampling clock signal CLK2, wherein said second sampling clock signal CLK2 is generated by an AND operation of the clock signal and the second flag signal FLAG2 provided by a second AND gate 14. On the other hand, the circuit structure shown in FIG. 3A and FIG. 3B is almost identical to that shown in FIG. 2A and FIG. 2B. The only difference is that the sampling circuits in FIG. 3A and FIG. 3B are falling-edge-triggered, and the related circuit elements and configurations are the same. In addition, it is further found that, in FIG. 2 and FIG. 3, the same circuit structure is adopted for both rising-edge sampling circuits and falling-edge sampling circuits, and such a circuit structure is different from our inventive circuit structure.
Please refer to FIG. 4, which is a general timing diagram of the conventional circuit shown in FIG. 2 and FIG. 3, wherein the first sampling clock signal CLK1 is proved to be obtained by an AND operation of the clock signal and the first flag signal FLAG1, and similarly the second sampling clock signal CLK2 is proved to be obtained by an AND operation of the clock signal and the second flag signal FLAG2. In FIG. 4, the data transfer is performed in a low-level region (labeled as “a”) of the timing of the clock signal, and the low-level region is limited to be within only half a clock cycle. Therefore, the first sampling clock signal CLK1 and the second sampling clock signal CLK2 remain unaffected because the transitions of the first flag signal FLAG1 and the second flag signal FLAG2 are performed in a low-level region.
FIG. 5 shows a timing diagram relative to that shown in FIG. 4. In the drawing, the error in high-speed operations of a general buffer circuit as shown in FIG. 2 and FIG. 3 has been illustrated, wherein the time interval between clock II and clock III is 0.6 ns. When the transitions of the first flag signal FLAG1 and the second flag signal FLAG2 occur during clock III, the excess pulse (labeled as “b”) may cause a certain amount of error data input into the buffer such that the incomplete pulse (labeled as “c”) may lead to an error of sampling data. In such a manner, the mentioned insufficient timing problem in that the error data are stored in the buffer occurs and may become more serious in high-speed data transfer operations. Moreover, in the prior art, the transitions of the flag signals can only be performed in a half-a-clock-cycle low-level region of the timing of the clock signal; otherwise, the excess pulse signal may cause an error storage of the data. Needless to say, there is a need for solving the problem.